Apparatus for receiving high-speed data in packet form

ABSTRACT

Apparatus for asynchronous reception of high-speed data in packet form in a receiver in a telecommunication system where transmitter and receiver are in communication in selected time slots over a common bus. The apparatus includes a delay line (7) receiving the incoming signal and having a plurality of taps, each of which feeds the signal to its own shift register. A locking circuit (10) is furthermore arranged, which stops the stepping forward in the shift register when the first &#34;one&#34; therein has come to a given position, and counting means (12) which senses this given position in each shift register and sums the sensed &#34;ones&#34;. A comparison circuit (14) compares the obtained sum with a value constituting the criterion for the number of sensed &#34;ones&#34; representing a received &#34;one&#34;.

This application is a continuation-in-part of application Ser. No.621,919 filed June 13, 1984, now abandoned.

BACKGROUND ART

A telecommunication system with high data transmission speed and wheredata is sent in packets with certain time intervals between the packets,e.g. a system operating with optical signals, necessitates specialmeasures for enabling comprehension and recognition of the value of thebit (a one or a zero) being received. In an optical telecommunicationsystem, e.g. that described in the report "COST 202 Seminar", September1981, the transmission speed is 100 Mbits/s, implying that the pulselength is 10 ns. Conventional methods in the reception of high speedpackets arriving at certain intervals requires clock supervision, whichpresupposes special coding and associated bandwith loss.

DISCLOSURE OF INVENTION

The basic idea of the invention is to provide an apparatus enablingsensing and storing of high-speed packets for subsequent reconstructionby a majority decision process.

More particularly, the invention contemplates apparatus for detectingthe binary value of pulse shaped signals which utilize a delay line forreceiving the pulse shaped signals with the delay line having Pequispaced taps. Each of P shift registers has an input connected to adifferent one of the taps as well as a stepping input and output. Aclock pulse source generates clock pulses to the stepping input of adifferent one of said shift registers. Each of a plurality of logicmeans is responsive to the presence of a one-bit at the output of adifferent shift register for activating the control means associatedwith the shift register. Sampling means has P inputs connectedrespectively to the outputs of the P shift registers for giving anindication of a particular binary value when more than a predeterminednumber of outputs of the P shift registers show a one-bit value.

DESCRIPTION OF FIGURES

The presently preferred embodiment of the invention will now bedescribed in detail with reference to the appended drawing, on which;

FIG. 1 is a block diagram of a digital communication system;

FIG. 2 is a signal diagram illustrating the shape of the signals insignalling between a sender and a receiver; and

FIG. 3 is a circuit diagram of the invention.

PREFERRED EMBODIMENT

FIG. 1 schematically illustrates an optical telecommunication systemhaving a plurality of terminals, e.g. 100 terminals, each of which isprovided with a transmitter 1 and a receiver 2. All transmitters andreceivers are connected to a common bus line 3 via connecting circuits 4and 5, which convert optical signals to electrical signals and viceversa, respectively. A sync generator 6 sends synchronizing signals overthe common bus so that they are available for all transmitters andreceivers. Transmission on the bus takes place at a rate of 100 Mbits/sand the frame is formed by 100 time slots, each corresponding to areceiver and are marked by the synchronizing bits. Each receiver isopened for the reception of data information with the aid of its clockin its reference position, which is a definite interval before thesynchronizing bit, and the transmitter selects the time slotcorresponding to the desired receiver. During this time slot, which hasa length of 32 bits, a data packet of 16 bits is sent in the middle ofthe time slot. Each time slot begins with a synchronizing bit, and wherea transmitter sends information to the receiver associated with the timeslot, the data packet follows 8 bits later on. No data packet follows inthe opposite case.

The signal diagram is illustrated in FIG. 2. The above mentionedtelecommunication system is described in the conference minutes from theCOST 202 Seminar, September 1981, and is not the subject of theinvention.

In a telecommunication system of the aforementioned type, it isdifficult to sense data signals with conventional means. The receivermust detect that the sync signal has arrived and it must also be able toidentify the contents of the data packet with respect to the bits, i.e.,ones and zeros. This can be performed with the aid of an apparatus inaccordance with the invention and which is illustrated in FIG. 3. Thesignals coming in over the bus line are fed to a delay line 7, which has10 taps 7-1 to 7-10 according to the embodiment. (Conversion of theoptical signals to electrical signals is performed in known manner, andtherefore only processing of the signals received and converted toelectrical signals is explained here.) The time period between thesignals fed out over two adjacent taps is 1 ns in the example. The tenoutput signals from the delay line 7 are each fed to its respectiveD-flipflop 8, the flipflops being controlled by a common clock (clock I)the phase of which is independent of incoming data. The clock I is fedto one input of gate 10 whose output is connected to the input of anassociated shift register. The output signals of the flipflops are eachfed with the aid of the same clock to a shift register 9 associated withthe respective flipflop. The clock signal clock I steps forward theinformation in the shift register, which consists of 30 stages forexample. The stepping forward is stopped when the information hasreached a given stage, the twentieth one of the example. This isobtained by the 1-signal from the last stage of the shift registerinhibiting gate 10 and thus preventing loading of the register. When thestepping forward in all shift registers has been stopped, the valuesfrom the last stages of the shift registers are read by clock II at alower rate than that of the input, e.g. at 10 MHz, with the aid ofparallel-to-serial converter 11 which unit increments a counter 12 foreach read-out "one".

If the condition is made that a received signal is to be regarded as a"one" if 6 of the 10 signals obtained from the delay line are a "one",the numeral 6 is set into a register 13. The values in the counter 12and register 13 are compared in a comparator 14, and when there isagreement an output signal from the comparator 14 is obtained as a signthat a one has been received. At the end of a bit time,a clearing pulsefrom sync generator 6 initializes the registers, inverter and counterpreparation to the reception of the next bit. The process is repeated anumber of times corresponding to the number of bits in the packet, oralternatively the reconstruction of the sync bit at low speed isutilized for obtaining a correct clock phase and register associatedwith this phase.

What is claimed is:
 1. Apparatus for detecting the binary value of pulseshaped signals comprising a delay line for receiving the pulse shapedsignals, said delay line having P equispaced taps; P shift registerseach having an input connected to a different one of said taps, astepping input and output; a clock pulse source for generating clockpulses; P control means each connected to said clock pulse source and tothe stepping input of a different one of said shift registers forcontrolling the passage of the clock pulses to said stepping input ofsaid different one of said shift registers; a plurality of means, eachof said means being responsive to the presence of a one-bit at theoutput of a different shift register for activating the control meansassociated with the shift register; and sampling means having P inputsconnected respectively to the outputs of said P shift registers forgiving an indication of a particular binary value when more than apredetermined number of outputs of said P shift registers show a one-bitvalue.
 2. The apparatus of claim 1 wherein said sampling means comprisescounting means of counting the number of one-bits at the outputs of saidP shift registers, a register means for storing a predetermined countnumber, and comparator means having first and second compare inputsconnected to said counter means and said register means respectively andan output for giving an indication that a pulse shaped signal has agiven binary value when the accumulated count in said counter means isgreater than the count number stored in said register means.
 3. Theapparatus of claim 2 wherein said counting means comprises aparallel/serial converter having P parallel inputs and a serial outputand stepped at a given rate and counting means connected to the serialoutput of said parallel/serial converter.
 4. Apparatus for detecting thebinary value of pulse shaped signals having a bit rate N comprising: adelay line for receiving the pulse shaped signals, said delay linehaving P equispaced taps; P shift registers each having an inputconnected to a different one of said taps, a stepping input and anoutput; a first clock pulse source for generating first clock pulses atsaid bit rate N; P control means each connected to said first clockpulse source and to the stepping input of a different one of said shiftregisters for controlling the passage of first clock pulses to saidstepping input of said different one of said shift registers; aplurality of means, each of said means being responsive to the presenceof a one-bit at the output of a different shift register for activatingthe control means associated with the shift register a parallel/serialconverter having P inputs, each connected to the output of a differentshift register, a stepping input and an output; a second clock pulsesource for generating second clock pulses at a bit rate less than N,said second clock pulse means connected to the stepping input of saidparallel/serial converter; a counter means connected to the output ofsaid parallel/serial converter for counting one-bits stored therein; aregister means for storing a predetermined count number and comparatormeans having first and second compare inputs connected to said countermeans and said register means respectively and an output for giving anindication that a pulse shaped signal has a given binary value when theaccumulated count in said means is greater than the count number storedin said register.